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april 2009 rev 6 1/17 17 vnb14n04 - vnk14n04fm vnv14n04 "omnifet" fully autoprotected power mosfet features n linear current limitation n thermal shutdown n short circuit protection n integrated clamp n low current drawn from input pin n diagnostic feedback through input pin n esd protection n direct access to the gate of the power mosfet (analog driving) n compatible with standard power mosfet description the vnb14n04, vnk14n04fm and vnv14n04 are monolithic devices made using stmicroeletronics vipower m0 technology, intended for replacement of standard power mosfets in dc to 50 khz applications. built-in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environment. fault feedback can be detected by monitoring the voltage at the input pin. type v clamp r ds(on) i lim vnb14n04 vnk14n04fm vnv14n04 42 v 42 v 42 v 0.07 w 0.07 w 0.07 w 14 a 14 a 14 a table 1. device summary part number order code vnb14n04 vnb14n04, VNB14N04-E, vnb14n0413tr, vnb14n04tr-e vnk14n04fm vnk14n04fm vnv14n04 vnv14n04, vnv14n04-e www.st.com
contents vnb14n04 - vnk14n04fm - vnv14n04 2/17 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
vnb14n04 - vnk14n04fm - vnv14n04 block diagram 3/17 1 block diagram figure 1. block diagram 1. powerso-10 pin configuration : input = 6,7,8,9,10 ; source = 1,2,4,5; drain = tab
electrical specification vnb14n04 - vnk14n04fm - vnv14n04 4/17 2 electrical specification 2.1 absolute maximum rating 2.2 thermal data 2.3 electrical characteristics t case =25 c unless otherwise specified. table 2. absolute maximum rating symbol parameter value unit powerso-10 d2pak sot-82fm v ds drain-source voltage (v in = 0) internally clamped v v in input voltage 18 v i d drain current internally limited a i r reverse dc output current -14 a v esd electrostatic discharge (c = 100 pf, r=1.5 k w ) 2000 v p tot total dissipation at t c = 25 c 50 9.5 w t j operating junction temperature internally limited c t c case operating temperature internally limited c t stg storage temperature -55 to 150 c table 3. thermal data symbol parameter powerso-10 sot82-fm d2pak unit r thj-case thermal resistance junction-case max 2.5 13 2.5 c/w r thj-amb thermal resistance junction-ambient max 50 100 62.5 c/w table 4. electrical characteristics symbol parameter test conditions min. typ. max. unit off v clamp drain-source clamp voltage i d = 200 ma v in = 0 36 42 48 v v clth drain-source clamp threshold voltage i d = 2 ma v in = 0 35 v v incl input-source reverse clamp voltage i in = -1 ma -1 -0.3 v
vnb14n04 - vnk14n04fm - vnv14n04 electrical specification 5/17 i dss zero input voltage drain current (v in = 0) v ds = 13 v v in = 0 v ds = 25 v v in = 0 50 200 a a i iss supply current from input pin v ds = 0 v v in = 10 v 250 500 a on (1) v in(th) input threshold voltage v ds = v in i d + i in = 1 ma 0.8 3 v r ds(on) static drain-source on resistance v in = 10 v i d = 7 a v in = 5 v i d = 7 a 0.7 0.1 ww dynamic g fs (1) forward transconductance v ds = 13 v i d = 7 a 8 10 s c oss output capacitance v ds = 13 v f = 1 mhz v in = 0 400 500 pf switching (2) t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 7 a v gen = 10 v r gen = 10 w (see figure 26 ) 60 160 250 100 120 300 400 200 ns ns ns ns t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 7 a v gen = 10 v r gen = 1000 w (see figure 26 ) 300 1.5 5.5 1.8 500 2.2 7.5 2.5 ns s s s (di/dt) on turn-on current slope v dd = 15 v i d = 7 a v in = 10 v r gen = 10 w 120 a/s q i total input charge v dd = 12 v i d = 7 a v in = 10 v 30 nc source drain diode v sd (1) forward on voltage i sd = 7 a v in = 0 1.6 v t rr (2) q rr (2) i rrm (2) reverse recovery time reverse recovery charge reverse recovery current i sd = 7 a di/dt = 100 a/s v dd = 30 v t j = 25 c (see test circuit, figure 28 ) 110 0.34 6.1 ns c a protection i lim drain current limit v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 10 10 14 14 20 20 aa t dlim (2) step response current limit v in = 10 v v in = 5 v 30 80 60 150 s s t jsh (2) overtemperature shutdown 150 c t jrs (2) overtemperature reset 135 c table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specification vnb14n04 - vnk14n04fm - vnv14n04 6/17 i gf (2) fault sink current v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 50 20 ma ma e as (2) single pulse avalanche energy starting t j = 25c v dd = 20 v v in = 10 v r gen = 1 k w l = 10 mh 0.65 j 1. pulsed: pulse duration = 300 s, duty cycle 1.5 % 2. parameters guaranteed by design/characterization table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
vnb14n04 - vnk14n04fm - vnv14n04 protection features 7/17 3 protection features during normal operation, the input pin is electrica lly connected to the gate of the internal power mosfet. the device then behaves like a standa rd power mosfet and can be used as a switch from dc to 50 khz. the only difference f rom the users standpoint is that a small dc current (i iss ) flows into the input pin in order to supply the i nternal circuitry. the device integrates: l overvoltage clamp protection: internally set at 42 v , along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. l linear current limiter circuit: limits the drain cu rrent id to ilim whatever the input pin voltage. when the current limiter is active, the de vice operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . l overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input volt age. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs at minimum 150 c. the device is automatically restarted when the chip temperatur e falls below 135 c. l status feedback: in the case of an overtemperature fault condition, a status feedback is provided through the input pin. the internal pro tection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 w . the failure can be detected by monitoring the volta ge at the input pin, which will be close to ground potential. additional features of this device are esd protecti on according to the human body model and the ability to be driven from a ttl logic circu it (with a small increase in r ds(on) ).
protection features vnb14n04 - vnk14n04fm - vnv14n04 8/17 figure 2. thermal impedance for d2pak/powerso-10 figure 3. derating curve figure 4. output characteristics figure 5. transconduc tance figure 6. static drain-source on resistance vs input voltage figure 7. static drain-source on resistance (part 1/2)
vnb14n04 - vnk14n04fm - vnv14n04 protection features 9/17 figure 8. static drain-source on resistance (part 2/2) figure 9. input charge vs input voltage figure 10. capacitance variations figure 11. normalize d input threshold voltage vs temperature figure 12. normalized on resistance vs temperature (part 1/2) figure 13. normalized on resistance vs temperature (part 2/2)
protection features vnb14n04 - vnk14n04fm - vnv14n04 10/17 figure 14. turn-on current slope(part 1/2) figure 15. turn-on current slope (part 2/2) figure 16. turn-off drain-source voltage slope (part 1/2) figure 17. turn-off drain-source voltage slope (part 2/2) figure 18. switching time resistive load (part 1/3) figure 19. switching time resistive load (part 2/3)
vnb14n04 - vnk14n04fm - vnv14n04 protection features 11/17 figure 20. switching time resistive load (part 3/3) figure 21. current limit vs junction temperature figure 22. step response current limit figure 23. sour ce drain diode forward characteristics
protection features vnb14n04 - vnk14n04fm - vnv14n04 12/17 figure 24. unclamped inductive load test circuits figure 25. unclamped inductive waveforms figure 26. switching times test circuits for resistive load figure 27. input charge test circuit figure 28. test circuit for inductive load switching and diode recovery times figure 29. waveforms
vnb14n04 - vnk14n04fm - vnv14n04 package information 13/17 4 package information in order to meet environmental requirements, st off ers these devices in different grades of ecopack ? packages, depending on their level of environmenta l compliance. ecopack ? specifications, grade definitions and product statu s are available at: www.st.com . ecopack ? is an st trademark. figure 30. to-263 (d2pak) mechanical data
package information vnb14n04 - vnk14n04fm - vnv14n04 14/17 figure 31. sot82-fm mechanical data
vnb14n04 - vnk14n04fm - vnv14n04 package information 15/17 figure 32. powerso-10 mechanical data
revision history vnb14n04 - vnk14n04fm - vnv14n04 16/17 5 revision history table 5. document revision history date revision changes 20-jan-1998 1 initial release. 21-jun-2004 5 update. 08-apr-2009 6 document reformatted. added table 1: device summary on page 1 . updated section 4: package information on page 13
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